This invention relates to digital signal processing (“DSP”) circuitry for use in programmable logic devices, and more particularly to DSP circuitry that can process multiple channels of data being transmitted on the same carrier.
Programmable logic devices (“PLDs”) are well known for their ability to perform any of a wide range of functions, depending on how they are programmed. Programming may be done by storing data in control bits on the PLD, by custom-configuring one or more layers of the materials used to fabricate the PLD, or by any other suitable means. Depending on the technology employed, the programming may be volatile or non-volatile, one-time-only or reprogrammable, etc.
In addition to the general-purpose circuitry typically included in the architecture of a PLD, it is also known to include various types of special-purpose circuitry in such devices. Examples of such special-purpose circuitry are blocks of memory, microprocessor circuitry, DSP circuitry, etc. Advantages of using special purpose circuitry is that they may be used to perform functions or process data independent of the programmable logic resources of the PLD, thus freeing those resources for other desired functions.
Consider, for example, existing DSP circuitry which can be used to perform common DSP task such as multiplication and filtering functions such as infinite impulse response filtering and finite impulse response filtering. Often times, it is desired that conventional DSP circuitry perform these task on multiple channels of data being carried on a single carrier. Providing multiple channels on a single carrier is known and is sometimes referred to as time division multiplexing (“TDM”). In multi-channel or TDM applications, each channel of data typically takes the form of a pulse modulation signal (e.g., pulse-amplitude modulation, pulse-width modulation, pulse-code modulation, etc.), which can be “interweaved” onto a signal carrier. This carrier signal is then transmitted to some type of circuitry that “unweaves” the multiple channels of data without mixing any of the channels.
When conventional DSP circuitry independently processes multiple channels of data on a single carrier, the channels often become mixed. That is, the data on one channel (e.g., channel 0) may be mixed with the data of another channel (e.g., channel 1), resulting in erroneous data processing. If multiple channels of data need to processed, using such conventional DSP circuitry, the conventional DSP circuitry needs to interact with tap delay lines. As known in the art, tap delay lines include circuitry that registers multiple channels of data and enables DSP circuitry to process each channel of data without experiencing cross-channel mixing.
Using this approach, however, requires that the tap delay lines be implemented using logic resources. Such use of logic resources is inefficient at least because those logic resources are being devoted to a tap delay line when they could better utilized in providing other desired functions.
It would therefore be desirable to provide DSP circuitry that can support multi-channel or time-division-multiplexing applications.
It would also be desirable to support multi-channel applications without requiring any utilization of logic resources.